As is well known, a non-volatile memory device such as a SD card is widely used in a variety of electronic devices. Generally, the non-volatile memory device comprises a memory array, and the memory array comprises plural cells. Each cell comprises a floating gate transistor. The floating gate transistor of each cell has a floating gate to store hot carriers. The storing state of the floating gate transistor may be determined according to the amount of the stored hot carriers.
Generally, after the hot carriers are injected into the floating gate transistor, a threshold voltage (VTH) of the floating gate transistor is changed according to the amount of the injected hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the non-volatile memory device, the threshold voltage of the floating gate transistor may be changed by controlling the amount of hot carriers to be injected into the floating gate. During a read cycle of the non-volatile memory device, a read voltage is provided to the floating gate transistor, and thus a cell current (also referred as a read current) is generated. According to the magnitude of the cell current, the storing state (e.g. an on state or an off state) of the floating gate transistor may be realized.
For example, if the read voltage is provided to the floating gate transistor with the lower threshold voltage, the floating gate transistor is in the on state to generate a higher cell current. Whereas, if the read voltage is provided to the floating gate transistor with the higher threshold voltage, the floating gate transistor is in the off state to generate a nearly-zero cell current. That is, during the read cycle, the on-state cell may generate a higher cell current, but the off-state cell may generate a lower cell current.
Moreover, the non-volatile memory device further comprises a current sensing amplifier for receiving the cell current from the cell, thereby determining the storing state of the cell.
FIG. 1 is a schematic circuit diagram illustrating a conventional current sensing amplifier. As shown in FIG. 1, the current sensing amplifier comprises three transistors M1, M2, M3, an operational amplifier OP, and a comparator CMP. The transistor M1 and the operational amplifier OP are collaboratively defined as a clamp circuit. The drain terminal of the transistor M1 is connected with a data line DL in order to receive a cell current Icell from the cell. The gate terminal of the transistor M1 is connected with the output terminal of the operational amplifier OP. The source terminal of the transistor M1 is connected with a low voltage source Vss. Moreover, a first input terminal of the operational amplifier OP receives an input voltage Vdl, and a second input terminal of the operational amplifier OP is connected with the drain terminal of the transistor M1. Consequently, in a normal working condition, the magnitude of the drain voltage V1 of the transistor M1 of the clamp circuit is equal to the magnitude of the input voltage Vdl.
Moreover, a bias voltage Vbias is received by the gate terminal of the transistor M3, and thus the transistor M3 is served as a current source to generate a reference current Iref. The reference current Iref is received by the drain terminal of the transistor M2. The gate terminal of the transistor M2 is connected with the gate terminal of the transistor M1. The source terminal of the transistor M2 is connected with the low voltage source Vss. A first input terminal of the comparator CMP is connected with the drain terminal of the transistor M2 for receiving the drain voltage V2 of the transistor M2. A second input terminal of the comparator CMP receives the input voltage Vdl. An output data is outputted from the output terminal of the comparator CMP.
During the read cycle, the data line DL is connected with the cell to receive the cell current. When the cell is in the on state, the magnitude of the cell current Icell is higher than the magnitude of the reference current Iref, and the drain voltage V2 of the transistor M2 is lower than the input voltage Vdl. Consequently, the comparator CMP issues a first logic level (e.g. a low level). On the other hand, when the cell is in the off state, the magnitude of the cell current Icell is lower than the magnitude of the reference current Iref, and the drain voltage V2 of the transistor M2 is higher than the input voltage Vdl. Consequently, the comparator CMP issues a second logic level (e.g. a high level).
From the above discussions, the conventional current sensing amplifier can determine the storing state of the cell according to the cell current Icell generated by the cell. However, since the conventional current sensing amplifier needs the operational amplifier OP, some drawbacks occur. For example, since a DC bias current should be provided to the operational amplifier OP during normally operating of the operational amplifier OP, the power consumption of the conventional current sensing amplifier is high.